Analysis of Interconnection Networks for Cache Coherent Multiprocessors with Scientific Applications

Interconnection networks, such as, shared bus and multistage interconnection networks (MINs) are very suitable for the design of shared memory multiprocessors. The existing analytical models of these networks are based on unrealistic synthetic workload for simplicity of the analyses. Also, they consider the networks in isolation without incorporating other architectural details of a multiprocessor. In this paper we present queueing network models for these interconnection networks for mul-tiprocessors with private cache memories. The multiprocessors operate with hardware cache coherence protocols and synchronization techniques. The models are based on single and multiple closed classes of customers. The input parameters for the queueing network are derived from an execution-driven simulation of some scientiic applications, These parameters include average instruction execution times, memory read and write request rates etc., and are diierent for diierent applications. The queueing network model is solved using simple mean value analysis (MVA) algorithms. The output parameters, like response time, are compared with those obtained from the simulator to show that the proposed queueing models are accurate.